1. Field of the Invention
The present invention relates to a reference voltage generation circuit, and more particularly relates to a reference voltage generation circuit that is still able to generate constant reference voltage and maintain a certain level of drive capability at the same time even when power supply voltage is relatively low.
2. Description of the Related Art
Reference voltage has been widely applied to electronic circuits, and plays a very important role in the electronic circuits; as a result, it would be desirable to provide a reference voltage generation circuit that is able to generate the reference voltage with high stability and has a certain level of drive capability at the same time.
FIG. 1 is a circuit diagram of a reference voltage generation circuit in conventional techniques. In the reference voltage generation circuit as shown in FIG. 1, VDDA refers to power supply voltage, and VREF refers to output voltage output from an output terminal of the reference voltage generation circuit. The basic principle of this reference voltage generation circuit is as follows.
A transistor ND1 refers to an N-channel depletion mode field effect transistor, and serves as an electric current source. When the transistor ND1 works in a saturation region, since the gate and the source of the transistor ND1 are connected to each other, drain current Id_ND1 flowing through the transistor ND1 is Id_ND1=K_ND1×(Vgs_ND1−Vth_ND1)2. Here Vgs_ND1 refers to voltage between the gate and the source of the transistor ND1; Vth_ND1 refers to threshold voltage of the transistor ND1; K_ND1=0.5×μn×Cox×W/L. Here μn refers to carrier mobility; W refers to channel width of the transistor ND1; L refers to channel length of the transistor ND1; and Cox refers to gate oxide capacitance per unit area.
A transistor N1 refers to an N-channel enhancement mode field effect transistor. When the transistor N1 works in a saturation region, drain current Id_N1 flowing through the transistor N1 is Id_N1=K_N1×(Vgs_N1−Vth_N1)2. Here Vgs_N1 refers to voltage between the gate and the source of the transistor N1; Vth_N1 refers to threshold voltage of the transistor N1; K_N1=0.5×μn×Cox×W/L. Here μn refers to carrier mobility; W refers to channel width of the transistor N1; L refers to channel length of the transistor N1; and Cox refers to gate oxide capacitance per unit area. Since the source of the transistor N1 is connected to ground, the voltage Vgs_N1 between the gate and the source of the transistor N1 is equal to gate voltage Vg_N1 of the transistor N1; as a result, the drain current Id_N1 flowing through the transistor N1 is Id_N1=K_N1×(Vg_N1−Vth_N1)2.
Transistors P1 and P2 form a current mirror circuit, so electric current flowing through the transistor P1 and electric current flowing through the transistor P2 are equal; in other words, the drain current Id_ND1 flowing through the transistor ND1 is equal to the drain current Id_N1 flowing through the transistor N1, i.e., K_ND1×(Vgs_ND1−Vth_ND1)2=K_N1×(Vg_N1−Vth_N1)2. As a result, Vg_N1=[(K1/K2)×(Vth_ND1)2]1/2+Vth_N1. Therefore it is apparent that the gate voltage Vg_N1 of the transistor N1 is constant voltage that is not influenced by the power supply voltage VDDA of the reference voltage generation circuit.
The output voltage VREF output from the output terminal of the reference voltage generation circuit is input into the gate of the transistor N1 as negative feedback voltage. After being compared with the gate voltage Vg_N1 of the transistor N1, the output voltage VREF is output from the gate of the transistor N1 to the transistor N2. And after being driven by the transistor N2, the output voltage VREF is output from the source of the transistor N2 to the output terminal of the reference voltage generation circuit so that the output voltage VREF output from the output terminal of the reference voltage generation circuit is stabilized at the level of the gate voltage of the transistor N1; at the same time, drive current is output from the transistor N2 to the output terminal of the reference voltage generation circuit so that the reference voltage generation circuit has a certain level of drive capability.
An ideal reference voltage generation circuit should be able to generate constant reference voltage and maintain a certain level of drive capability at the same time without receiving influence from power supply voltage. However, in the reference voltage generation circuit shown in FIG. 1, the output voltage VREF output from the output terminal of the reference voltage generation circuit may be influenced by open loop gain of the reference voltage generation circuit, i.e., VREF=Vg_N1/(1+1/Av). Here Av refers to the open loop gain of the reference voltage generation circuit, and is composed of two parts: Av1≈gm_N1×(gm_P4+gmb_P4)×r0_P4×r0_P2 and Av2≈gm_N2/((Iout/VREF)+gm_N2); that is, Av=Av1×Av2. Here gm_N1 refers to transconductance of the transistor N1; gm_P4 refers to transconductance of transistor P4; gmb_P4 refers to body effect transconductance of the transistor P4; r0_P4 refers to equivalent resistance of the transistor P4; r0_P2 refers to equivalent resistance of the transistor P2; gm_N2 refers to transconductance of the transistor N2; Iout refers to drive current output from the output terminal of the reference voltage generation circuit; and VREF refers to the output voltage output from the output terminal of the reference voltage generation circuit. Since Av2≈1, Av≈Av1, i.e., Av≈gm_N1×(gm_P4+gmb_P4)×r0_P4×r0_P2. In an ideal circumstance, the open loop gain of the reference voltage generation circuit approaches infinity; as a result, the output voltage VREF output from the output terminal of the reference voltage generation circuit is able to be stabilized at the level of the gate voltage of the transistor N1. However, when the power supply voltage drops to a relatively low value, in a case where the drive current output from the transistor N2 to the output terminal of the reference voltage generation circuit is maintained without change, the gate voltage of the transistor N2 is maintained without change too; as a result, voltage between the power supply voltage and the gate of the transistor N2 drops because the power supply voltage drops. That is, voltage between the source and the drain of the transistors P2 and P4 drops so that the transistors P2 and P4 enter a linear region from the saturation region. After the transistors P2 and P4 enter the linear region from the saturation region, the transconductance and the equivalent resistance of the transistors P2 and P4 become small so that the open loop gain Av of the reference voltage generation circuit apparently drops; as a result, the output voltage VREF output from the output terminal of the reference voltage generation circuit drops. Therefore it is apparent that when the power supply voltage drops to a relatively low value, the above-mentioned conventional reference voltage generation circuit shown in FIG. 1 is not able to generate constant reference voltage and maintain a certain level of drive capability at the same time.